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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBusTM Four-Host PCI-to-USB OpenHCI Host Controller
Features
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Description
The Agere Systems Inc. USS-344 QuadraBus provides a single-chip four-host PCI-to-Universal Serial Bus (USB) solution. The USS-344 interfaces directly to any 32-bit, 33 MHz PCI bus and is ideal for either onboard applications or add-in card applications. It can easily be configured to communicate in either a 3 V PCI environment or 5 V PCI environment simply by selecting the appropriate communications voltage level on the VIO input pin. The USS-344 provides four downstream USB ports for connectivity with any USB compliant device or hub. Fullspeed or low-speed peripherals are supported along with all of the USB transfer types: control, interrupt, bulk, or isochronous. The USS-344's OpenHCI compliance offers significant USB performance benefits and reduced CPU overhead compared to other USB UHCI host controllers. In addition, the USS-344 offers a significant performance advantage over all other USB host controllers (both UHCI and OHCI) by providing full USB bandwidth to each port rather than sharing the USB bandwidth over all ports. This results in an increase in the number of devices which can feasibly be connected to a computer system as well as ensuring high-bandwidth devices, such as video cameras and audio devices, are always provided with the high bandwidth they need while other USB devices are in use. The USS-344 is a multifunction PCI device with one single-port USB host controller per PCI function. There are four PCI functions in the USS-344 for a total of four single-port USB host controllers. Each single-port host controller provides the full USB bandwidth (12 Mbits/s) for devices connected downstream of its port. The USS-344 is fully compatible with the Microsoft Windows standard OpenHCI drivers. The USS-344 pinout is compatible with the future release of the Agere USB 2.0 host controller.The USS-344 is a 3.3 V device fabricated in 0.25 m technology. Integrated dual-speed USB transceivers enable a single-chip PCI-to-USB solution. The USS-344 provides full support for legacy PC peripherals as defined in the OpenHCI Open Host Controller Interface Specification for USB Release 1.0a.
* Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation. Mac is a registered trademark of Apple Computer, Inc.
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32-bit, 33 MHz PCI interface compliant with PCI Local Bus Specification Revision 2.2 Four downstream USB ports Each USB port dedicated to providing full USB bandwidth to the attached device Full compliance with Universal Serial Bus Specification Revision 1.1 OpenHCI Open Host Controller Interface Specification for USB Release 1.0a compatible Fully compatible with Microsoft Windows 98/95/Windows NT * standard OpenHCI drivers Fully compatible with Mac OS 8.5 and 8.6 Integrated dual-speed USB transceivers 3 V or 5 V switchable PCI signaling Low-power mode and wake-up compatible with PCI Power Management Interface Specification Revision 1.1 Supports up to 127 devices per port Supports peripheral hot swap and wake-up Support for legacy keyboard and mouse 128-pin TQFP package Full 12 Mbits/s bandwidth per port Evaluation kit: -- PCI card -- Data sheet 0.25 m technology
Applications
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Seamless integration with 3 V or 5 V PCI-based computer products Supports all USB compliant devices and hubs Simultaneous operation of multiple high-performance devices
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Table of Contents
Contents Page
Features .................................................................................................................................................................. 1 Applications ............................................................................................................................................................. 1 Description ............................................................................................................................................................... 1 Applicable Documents and Specifications ............................................................................................................... 4 Pin Information ........................................................................................................................................................ 4 Register Overview ................................................................................................................................................... 8 PCI Registers ........................................................................................................................................................ 12 PCI Function 0--Single-Port USB Host Controller 0 .......................................................................................12 PCI Function 1--Single-Port USB Host Controller 1 .......................................................................................16 PCI Function 2--Single-Port USB Host Controller 2 .......................................................................................20 PCI Function 3--Single-Port USB Host Controller 3 .......................................................................................24 USB Registers ....................................................................................................................................................... 28 Legacy Support Registers ..................................................................................................................................... 35 HceInput Register ............................................................................................................................................35 HceOutput Register .........................................................................................................................................36 HceStatus Register..........................................................................................................................................36 HceControl Register ........................................................................................................................................37 Connection Instructions ......................................................................................................................................... 37 PCI Connection Instructions ............................................................................................................................37 USB Connection Instructions...........................................................................................................................38 Test Mode Connection Instructions .................................................................................................................38 Legacy Configuration ............................................................................................................................................. 40 Power Connection Recommendations .................................................................................................................. 41 Power Management Interface ............................................................................................................................... 42 Configuration Space Offset 50h.......................................................................................................................43 Configuration Space Offset 51h.......................................................................................................................43 Configuration Space Offset 52h.......................................................................................................................44 Configuration Space Offset 54h.......................................................................................................................44 Configuration Space Offset 56h.......................................................................................................................45 Configuration Space Offset 57h.......................................................................................................................45 Power Consumption/Dissipation Reporting .....................................................................................................45 NAND Tree Mode .................................................................................................................................................. 46 Absolute Maximum Ratings ................................................................................................................................... 48 Electrical Characteristics ....................................................................................................................................... 49 PCI Electrical Characteristics ..........................................................................................................................49 USB Electrical Characteristics .........................................................................................................................52 Physical Markings .................................................................................................................................................. 53 Outline Diagram ..................................................................................................................................................... 53 128-Pin TQFP..................................................................................................................................................53 Ordering Information .............................................................................................................................................. 54
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Description (continued)
USS-344 PCI-TO-USB OpenHCI HOST CONTROLLER
ADDRESS DATA CONTROL HCI SLAVE BLOCK
USB STATE CONTROL
ROOT HUB AND HOST SIE
TX
OHCI ROOT HUB PORT 1
DATA ADDRESS/ DATA CONTROL HCI MASTER BLOCK
LIST PROCESSOR BLOCK HSIE S/M FIFO DPLL RX
MIRQ121 KIRQ1I A20I IRQ1 IRQ12 A20MN SMIN CLK48STOP PMEN
LEGACY SUPPORT
POWER MNGMNT LOGIC
POWER MNGMNT PCI CORE 0
LEGACY LOGIC USB HOST CONTROLLER CORE 0
USB
AD[31:0] CBE[3:0] REQN GNTN IDSEL FRAMEN IRDYN TRDYN DEVSELN STOPN PERRN SERRN PAR INTA INTB INTC INTD
POWER MNGMNT PCI ARBITER PCI CORE 1
LEGACY LOGIC USB HOST CONTROLLER CORE 1
USB
PCI BUS
POWER MNGMNT PCI CORE 2
LEGACY LOGIC USB HOST CONTROLLER CORE 2
USB
POWER MNGMNT PCI CORE 3
LEGACY LOGIC USB HOST CONTROLLER CORE 3
USB
5-7828.r1
Figure 1. USS-344 Interconnection Diagram
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Applicable Documents and Specifications
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PCI Local Bus Specification Revision 2.1s., June 1, 1995. PCI Special Interest Group. Universal Serial Bus Specification Revision 1.1., September 23, 1998. Compaq/Digital Equipment Corporation/ IBM PC Company/Intel/Microsoft/NEC/Northern Telecom. OpenHCI Open Host Controller Interface Specification for USB Release 1.0a., July 31, 1997. Compaq/Microsoft/ National Semiconductor. PCI Bus Power Management Interface Specification Revision 1.1., December 18, 1998. PCI Special Interest Group.
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Pin Information
AD25 AD26 AD27 AD28 VDD VSS AD29 AD30 AD31 PMEN VDD VSS REQN GNTN VSS CLK VDD RSTN INTDN INTCN INTBN VSS VDD INTAN PWRFLT3N PRTPWR3 VDD VSS AD24 C/BEN3 IDSEL AD23 AD22 VSS VDD AD21 AD20 AD19 AD18 VSS VDD AD17 AD16 C/BEN2 FRAMEN VDD VSS IRDYN TRDYN DEVSELN STOPN PERRN VSS VDD SERRN PAR C/BEN1 AD15 VDD VSS AD14 AD13 AD12 AD11 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
USS-344
PWRFLT2N PRTPWR2 VSST VDDT DMNS3 DPLS3 DMNS2 DPLS2 VSST VDDT DMNS1 DPLS1 DMNS0 DPLS0 VSST VDDT RREF VDDA XHI XLO/CLK48 VSSA CLK48STOP VDD PWRFLT1N PRTPWR1 PWRFLT0N PRTPWR0 SMIN VSS VDD IRQ12 IRQ1 A20MN A20I KIRQ1I MIRQ12I VSS VDD
VDD VSS AD10 AD9 AD8 C/BEN0 VSS VDD AD7 AD6 AD5 AD4 VSS VDD AD3 AD2 AD1 AD0 VSS VIO VDD VSS TEST0 TEST1 TEST2 TEST3
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
5-7830
Figure 2. USS-344 Pin Diagram
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 1. Numeric Pin Cross Reference Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol* VDD VSS AD24 C/BEN3 IDSEL AD23 AD22 VSS VDD AD21 AD20 AD19 AD18 VSS VDD AD17 AD16 C/BEN2 FRAMEN VDD VSS IRDYN TRDYN DEVSELN STOPN PERRN VSS VDD SERRN PAR C/BEN1 AD15 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol* VDD VSS AD14 AD13 AD12 AD11 VDD VSS AD10 AD9 AD8 C/BEN0 VSS VDD AD7 AD6 AD5 AD4 VSS VDD AD3 AD2 AD1 AD0 VSS VIO VDD VSS TEST0 TEST1 TEST2 TEST3 Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Symbol* VDD VSS MIRQ12I KIRQ1I A20I A20MN IRQ1 IRQ12 VDD VSS SMIN PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N VDD CLK48STOP VSSA XLO/CLK48 XHI VDDA RREF VDDT VSST DPLS0 DMNS0 DPLS1 DMNS1 VDDT VSST DPLS2 DMNS2 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Symbol* DPLS3 DMNS3 VDDT VSST PRTPWR2 PWRFLT2N PRTPWR3 PWRFLT3N INTAN VDD VSS INTBN INTCN INTDN RSTN VDD CLK VSS GNTN REQN VSS VDD PMEN AD31 AD30 AD29 VSS VDD AD28 AD27 AD26 AD25
* Pins identified as NC are unused and should be left unconnected. Active-low signals within this document are indicated by an N following the symbol names.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Pin Information (continued)
Table 2. PCI Signals Pin Symbol* Type Description 111 RSTN Input PCI Reset (Active-Low). 113 CLK Input PCI System Clock (33 MHz). 116 REQN Output/3-State PCI Request (Active-Low). 115 GNTN Input PCI Grant (Active-Low). Bidir PCI Address and Data. 120, 121, 122, 125, 126, 127, 128, AD[31:0] 3, 6, 7, 10, 11, 12, 13, 16, 17, 32, 35, 36, 37, 38, 41, 42, 43, 47, 48, 49, 50, 53, 54, 55, 56 30 PAR Bidir PCI Parity. 4, 18, 31, 44 C/BEN[3:0] Bidir PCI Bus Command and Byte Enables. 19 FRAMEN Bidir PCI Cycle Frame (Active-Low). 22 IRDYN Bidir PCI Initiator Ready (Active-Low). 23 TRDYN Bidir PCI Target Ready (Active-Low). 25 STOPN Bidir PCI Stop (Active-Low). 5 IDSEL Input PCI Initialization Device Select. 24 DEVSELN Bidir PCI Device Select (Active-Low). 26 PERRN Bidir PCI Parity Error (Active-Low). 29 SERRN Output/Open Drain PCI System Error (Active-Low). 105 INTAN Output/Open Drain PCI Interrupt A (Active-Low). 108 INTBN Output/Open Drain PCI Interrupt B (Active-Low). 109 INTCN Output/Open Drain PCI Interrupt C (Active-Low). 110 INTDN Output/Open Drain PCI Interrupt D (Active-Low). 119 PMEN Output/Open Drain Power Management Event (Active-Low). 1, 9, 15, 20, 28, 33, 39, 46, 52, 59, VDD Power 3.3 V VDD. 65, 73, 80, 106, 112, 118, 124 2, 8, 14, 21, 27, 34, 40, 45, 51, 57, VSS Power VSS. 60, 66, 74, 107, 114, 117, 123 58 VIO Power PCI Environment Selection (3.3 V or 5 V).
* An N following the symbol names indicates active-low for the USS-344.
Table 3. USB Port Signals Pin 89 90 91 92 95 96 97 98 76 78 101 103 Symbol* DPLS0 DMNS0 DPLS1 DMNS1 DPLS2 DMNS2 DPLS3 DMNS3 PRTPWR0 PRTPWR1 PRTPWR2 PRTPWR3 Type Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Description USB Port 0 DPLUS. USB Port 0 DMINUS. USB Port 1 DPLUS. USB Port 1 DMINUS. USB Port 2 DPLUS. USB Port 2 DMINUS. USB Port 3 DPLUS. USB Port 3 DMINUS. USB Port 0 Power Enable (Active-Low). USB Port 1 Power Enable (Active-Low). USB Port 2 Power Enable (Active-Low). USB Port 3 Power Enable (Active-Low).
* An N following the symbol names indicates active-low for the USS-344.
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Pin Information (continued)
Table 3. USB Port Signals (continued) Pin 77 79 102 104 81 87, 93, 99 88, 94, 100 86 85 82 84 83 Symbol* PWRFLT0N PWRFLT1N PWRFLT2N PWRFLT3N CLK48STOP VDDT VSST RREF VDDA VSSA XHI XLO/CLK48 Type Input Input Input Input Bidir Power Power Input Power Power Power Power/Input Description USB Port 0 Overcurrent (Active-Low). USB Port 1 Overcurrent (Active-Low). USB Port 2 Overcurrent (Active-Low). USB Port 3 Overcurrent (Active-Low). USB Clock Stop (Optional). Used to stop external 48 MHz clock in PCI power management state D3. USB Transceiver VDD (3.3 V). USB Transceiver VSS. USB 2.0 1 k Precision Resistor Connection. Hi-Z if implementation does not expect upgrade to USB 2.0. USB 2.0 Analog Power. Connect to VDD if implementation does not expect upgrade to USB 2.0. USB 2.0 Analog Power. Connect to VSS if implementation does not expect upgrade to USB 2.0. USB 2.0 Crystal Oscillator XHI Connection. Hi-Z if implementation does not expect upgrade to USB 2.0. USB 2.0 Crystal Oscillator XHI Connection/USB 1.X CLK 48 MHz Input.
* An N following the symbol names indicates active-low for the USS-344.
Table 4. Legacy Support Signals Pin 68 67 69 70 71 72 75 Symbol* KIRQ1I MIRQ12I A20I A20MN IRQ1 IRQ12 SMIN Type Input Input Input Output/Open Drain Output/Open Drain Output/Open Drain Output/Open Drain Description Legacy Keyboard Controller Interrupt (IRQ1 Input from Keyboard Controller). Legacy Mouse Controller Interrupt (IRQ12 Input from Mouse Controller). Legacy Gate A20 Input. Legacy Gate A20 Output (to Memory Controller). System Keyboard Interrupt (Active-High). System Mouse Interrupt (Active-High). System Management Interrupt (Active-Low).
* An N following the symbol names indicates active-low for the USS-344.
Table 5. Chip Test Signals Pin 61 62 63 64 Symbol* TEST0 TEST1 TEST2 TEST3 Type Input Input Input Input Description Chip Test Signal. Refer to Test Mode Connection Instructions section for usage information. Chip Test Signal. Refer to Test Mode Connection Instructions section for usage information. Chip Test Signal. Refer to Test Mode Connection Instructions section for usage information. Chip Test Signal. Refer to section Test Mode Connection Instructions for usage information.
* An N following the symbol names indicates active-low for the USS-344.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Register Overview
Table 6. PCI Bus Configuration Memory Summary (Function 0) Refer to Tables 10--31 for more details on each of these registers. Configuration Space Offset 00h--01h 02h--03h 04h--05h 06h--07h 08h 09h--0Bh 0Ch 0Dh 0Eh 0Fh 10h--13h 14h--17h 18h--1Bh 1Ch--1Fh 20h--23h 24h--27h 28h--2Bh 2Ch--2Dh 2Eh--2Fh 30h--33h 34h 3Ch 3Dh 3Eh 3Fh 4Ch Vendor ID Device ID Command Status Revision ID* Class Code Cache Line Size Latency Timer Header Type BIST BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 CardBus CIS Pointer Subsystem Vendor ID Subsystem ID Expansion ROM Base Address Capabilities Pointer Interrupt Line Interrupt Pin Min_Gnt Max_Lat Special--Subsystem Write Capability Register Name Read/Write R R R/W R/W R R R R/W R R R/W R R R R R R R/W R/W R R R/W R R R R/W Default Value (Reset) 11C1h 5803h 0000h TEST1 = 0b: 0210h TEST1 = 1b: 0200h 10h 0C0310h 00h 00h 80h 00h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 11C1h 5803h 00000000h TEST1 = 0b: 50h TEST1 = 1b: 00h 00h 01h 03h 56h 00000000h
* The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision. This register is normally read only. Write capability of this register is available to system BIOS only.
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Register Overview (continued)
Table 7. PCI Bus Configuration Memory Summary (Function 1) Refer to Tables 32--53 for more details on each of these registers. Configuration Space Offset 00h--01h 02h--03h 04h--05h 06h--07h 08h 09h--0Bh 0Ch 0Dh 0Eh 0Fh 10h--13h 14h--17h 18h--1Bh 1Ch--1Fh 20h--23h 24h--27h 28h--2Bh 2Ch--2Dh 2Eh--2Fh 30h--33h 34h 3Ch 3Dh 3Eh 3Fh 4Ch Vendor ID Device ID Command Status Revision ID* Class Code Cache Line Size Latency Timer Header Type BIST BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 CardBus CIS Pointer Subsystem Vendor ID Subsystem ID Expansion ROM Base Address Capabilities Pointer Interrupt Line Interrupt Pin Min_Gnt Max_Lat Special--Subsystem Write Capability Register Name Read/Write R R R/W R/W R R R R/W R R R/W R R R R R R R/W R/W R R R/W R R R R/W Default Value (Reset) 11C1h 5803h 0000h TEST1 = 0b: 0210h TEST1 = 1b: 0200h 10h 0C0310h 00h 00h 80h 00h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 11C1h 5803h 00000000h TEST1 = 0b: 50h TEST1 = 1b: 00h 00h TEST0 = 0b: 01h TEST0 = 1b: 02h 03h 56h 00000000h
* The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision. This register is normally read only. Write capability of this register is available to system BIOS only.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Register Overview (continued)
Table 8. PCI Bus Configuration Memory Summary (Function 2) Refer to Tables 54--75 for more details on each of these registers. Configuration Space Offset 00h--01h 02h--03h 04h--05h 06h--07h 08h 09h--0Bh 0Ch 0Dh 0Eh 0Fh 10h--13h 14h--17h 18h--1Bh 1Ch--1Fh 20h--23h 24h--27h 28h--2Bh 2Ch--2Dh 2Eh--2Fh 30h--33h 34h 3Ch 3Dh 3Eh 3Fh 4Ch Vendor ID Device ID Command Status Revision ID* Class Code Cache Line Size Latency Timer Header Type BIST BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 CardBus CIS Pointer Subsystem Vendor ID Subsystem ID Expansion ROM Base Address Capabilities Pointer Interrupt Line Interrupt Pin Min_Gnt Max_Lat Special--Subsystem Write Capability Register Name Read/Write R R R/W R/W R R R R/W R R R/W R R R R R R R/W R/W R R R/W R R R R/W Default Value (Reset) 11C1h 5803h 0000h TEST1 = 0b: 0210h TEST1 = 1b: 0200h 10h 0C0310h 00h 00h 80h 00h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 11C1h 5803h 00000000h TEST1 = 0b: 50h TEST1 = 1b: 00h 00h TEST0 = 0b: 01h TEST0 = 1b: 03h 03h 56h 00000000h
* The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision. This register is normally read only. Write capability of this register is available to system BIOS only.
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Register Overview (continued)
Table 9. PCI Bus Configuration Memory Summary (Function 3) Refer to Tables 76--97 for more details on each of these registers. Configuration Space Offset 00h--01h 02h--03h 04h--05h 06h--07h 08h 09h--0Bh 0Ch 0Dh 0Eh 0Fh 10h--13h 14h--17h 18h--1Bh 1Ch--1Fh 20h--23h 24h--27h 28h--2Bh 2Ch--2Dh 2Eh--2Fh 30h--33h 34h 3Ch 3Dh 3Eh 3Fh 4Ch Vendor ID Device ID Command Status Revision ID* Class Code Cache Line Size Latency Timer Header Type BIST BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 CardBus CIS Pointer Subsystem Vendor ID Subsystem ID Expansion ROM Base Address Capabilities Pointer Interrupt Line Interrupt Pin Min_Gnt Max_Lat Special--Subsystem Write Capability Register Name Read/Write R R R/W R/W R R R R/W R R R/W R R R R R R R/W R/W R R R/W R R R R/W Default Value (Reset) 11C1h 5803h 0000h TEST1 = 0b: 0210h TEST1 = 1b: 0200h 10h 0C0310h 00h 00h 80h 00h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 11C1h 5803h 00000000h TEST1 = 0b: 50h TEST1 = 1b: 00h 00h TEST0 = 0b: 01h TEST0 = 1b: 04h 03h 56h 00000000h
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (T) and Y will identify the revision. This register is normally read only. Write capability of this register is available to system BIOS only.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
PCI Registers
PCI Function 0--Single-Port USB Host Controller 0
Table 10. Vendor ID Register (00h--01h) This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG. Bits 15:0 Field Vendor ID Read/Write R Reset/Description Assigned 11C1h
Table 11. Device ID Register (02h--03h) This register is fixed as the Agere Systems product USS-344. Bits 15:0 Field Device ID Read/Write R Reset/Description Assigned 5803h
Table 12. Command Register (04h--05h) All read-only bits represent nonconfigurable features of the USS-344. Bits 0 1 2 3 4 5 6 7 8 9 15:10 Field IO Space Memory Space Bus Master Special Cycles Memory Write and Invalidate Enable VGA Palette Snoop Parity Error Response Wait Cycle Control SERRN Enable Fast Back-to-back Enable Reserved Read/Write R/W R/W R/W R R/W R R/W R R/W R/W R 0 0 0 0 0 0 0 0 0 0 000000b Reset/Description
Table 13. Status Register (06h--07h) All read-only bits represent nonconfigurable features of the USS-344. Bits 3:0 4 5 6 7 8 10:9 11 12 13 14 15 12 Field Reserved Capabilities 66 MHz Capable UDF Support Fast Back-to-back Capable Data Parity Error Detected DEVSEL Timing Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Read/Write R R R R R R/W R R/W R/W R/W R/W R/W Reset/Description 0000b TEST1 = 0b: 1 TEST1 = 1b: 0 0 0 0 0 01 0 0 0 0 0 Agere Systems Inc.
Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 14. Revision ID Register (08h) Represents the current revision of the USS-344. Bits 7:0 Field Revision ID* R Read/Write 10h Reset/Description
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 15. Class Code Register (09h--0Bh) The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification. Bits 7:0 15:8 23:16 Field Programming Interface R Subclass R Base Class R Read/Write Reset/Description 10h = OpenHCI Host Controller 03h = Universal Serial Bus 0Ch = Serial Bus Controller
Table 16. Cache Line Size Register (0Ch) No cache line is supported by the USS-344. Bits 7:0 Field Cache Line Size R Read/Write 00h Reset/Description
Table 17. Latency Timer Register (0Dh) Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master. Bits 7:0 Field Latency Timer R/W Read/Write Reset/Description Upper 5 bits are read/write. Lower 3 bits are read only.
Table 18. Header Type Register (0Eh) The USS-344 supports PCI header type 0 only. Bits 7:0 Field Header Type R Read/Write Reset/Description 80h = Multifunction PCI Device
Table 19. BIST Register (0Fh) BIST is not supported by the USS-344. Bits 7:0 BIST Field R Read/Write 00h Reset/Description
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
Table 20. Base Address Register 0 (10h--13h) The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device. As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K (212) memory size. Bits 31:0 BAR 0 Field R/W Read/Write Reset/Description Lower 12 bits are read only. Upper 20 bits are read/write.
Table 21. Base Address Register 1, 2, 3, 4, 5 (14h--17h), (18h--1Bh), (1Ch--1Fh), (20h--23h), (24h--27h) These Base Address registers are unused by the USS-344 device. Bits 31:0 Field BAR 1--5 R Read/Write Reset/Description 00000000h
Table 22. Cardbus CIS Pointer Register (28h--2Bh) Cardbus CIS pointer not required for the USS-344. Bits 31:0 Field CardBus CIS Pointer R Read/Write Reset/Description 00000000h
Table 23. Subsystem Vendor ID Register (2Ch--2Dh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem Vendor ID R/W Read/Write 11C1h Reset/Description
Table 24. Subsystem ID Register (2Eh--2Fh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem ID R/W Read/Write 5803h Reset/Description
Table 25. Expansion ROM Base Address Register (30h--33h) Expansion ROM not supported by the USS-344. Bits 31:0 Field Expansion ROM Base Address R Read/Write Reset/Description 00000000h
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 26. Capabilities Pointer Register (34h) Bits 7:0 Cap_Ptr Field R Read/Write Reset/Description TEST1 = 0b: 50h TEST1 = 1b: 00h
Table 27. Interrupt Line Register (3Ch) Bits 7:0 Field Interrupt Line R/W Read/Write 00h Reset/Description
Table 28. Interrupt Pin Register (3Dh) Interrupt A used as the PCI interrupt for this core. Bits 7:0 Field Interrupt Pin R Read/Write 01h Reset/Description
Table 29. Min_Gnt Register (3Eh) The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns. Bits 7:0 Min_Gnt Field R Read/Write 03h Reset/Description
Table 30. Max_Lat Register (3Fh) The USS-344 requires service at a minimum interval of 21.3 s. Bits 7:0 Max_Lat Field R Read/Write 56h Reset/Description
Table 31. Special--Subsystem Write Capability (4Ch) This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0 is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID registers (refer to Tables 23 and 24). Bits 31:1 0 Field Reserved Subsystem Write R R/W Read/Write Reset/Description 00000000h 0b 0 = Subsystem write disabled 1 = Subsystem write enabled
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
PCI Function 1--Single-Port USB Host Controller 1
Table 32. Vendor ID Register (00h--01h) This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG. Bits 15:0 Vendor ID Field R Read/Write Reset/Description Assigned 11C1h
Table 33. Device ID Register (02h--03h) This register is fixed as the Agere Systems product USS-344. Bits 15:0 Device ID Field R Read/Write Reset/Description Assigned 5803h
Table 34. Command Register (04h--05h) All read-only bits represent nonconfigurable features of the USS-344. Bits 0 1 2 3 4 5 6 7 8 9 15:10 Field IO Space Memory Space Bus Master Special Cycles Memory Write and Invalidate Enable VGA Palette Snoop Parity Error Response Wait Cycle Control SERRN Enable Fast Back-to-back Enable Reserved R/W R/W R/W R R/W R R/W R R/W R/W R Read/Write 0 0 0 0 0 0 0 0 0 0 000000b Reset/Description
Table 35. Status Register (06h--07h) All read-only bits represent nonconfigurable features of the USS-344. Bits 3:0 4 5 6 7 8 10:9 11 12 13 14 15 16 Reserved Capabilities 66 MHz Capable UDF Support Fast Back-to-back Capable Data Parity Error Detected DEVSEL Timing Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Field R R R R R R/W R R/W R/W R/W R/W R/W Read/Write Reset/Description 0000b TEST1 = 0b: 1 TEST1 = 1b: 0 0 0 0 0 01 0 0 0 0 0 Agere Systems Inc.
Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 36. Revision ID Register (08h) Represents the current revision of the USS-344. Bits 7:0 Field Revision ID* R Read/Write 10h Reset/Description
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 37. Class Code Register (09h--0Bh) The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification. Bits 7:0 15:8 23:16 Field Programming Interface R Subclass R Base Class R Read/Write Reset/Description 10h = OpenHCI Host Controller 03h = Universal Serial Bus 0Ch = Serial Bus Controller
Table 38. Cache Line Size Register (0Ch) No cache line is supported by the USS-344. Bits 7:0 Field Cache Line Size R Read/Write 00h Reset/Description
Table 39. Latency Timer Register (0Dh) Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master. Bits 7:0 Field Latency Timer R/W Read/Write Reset/Description Upper 5 bits are read/write. Lower 3 bits are read only.
Table 40. Header Type Register (0Eh) The USS-344 supports PCI header type 0 only. Bits 7:0 Field Header Type R Read/Write Reset/Description 80h = Multifunction PCI Device
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Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
Table 41. BIST Register (0Fh) BIST is not supported by the USS-344. Bits 7:0 BIST Field R Read/Write 00h Reset/Description
Table 42. Base Address Register 0 (10h--13h) The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device. As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K (212) memory size. Bits 31:0 BAR 0 Field R/W Read/Write Reset/Description Lower 12 bits are read only. Upper 20 bits are read/write.
Table 43. Base Address Register 1, 2, 3, 4, 5 (14h--17h), (18h--1Bh), (1Ch--1Fh), (20h--23h), (24h--27h) These Base Address registers are unused by the USS-344 device. Bits 31:0 Field BAR 1--5 R Read/Write Reset/Description 00000000h
Table 44. Cardbus CIS Pointer Register (28h--2Bh) Cardbus CIS pointer not required for the USS-344. Bits 31:0 Field CardBus CIS Pointer R Read/Write Reset/Description 00000000h
Table 45. Subsystem Vendor ID Register (2Ch--2Dh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem Vendor ID R/W Read/Write 11C1h Reset/Description
Table 46. Subsystem ID Register (2Eh--2Fh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem ID R/W Read/Write 5803h Reset/Description
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 47. Expansion ROM Base Address Register (30h--33h) Expansion ROM not supported by the USS-344. Bits 31:0 Field Expansion ROM Base Address R Read/Write Reset/Description 00000000h
Table 48. Capabilities Pointer Register (34h) Bits 7:0 Cap_Ptr Field R Read/Write Reset/Description TEST1 = 0b: 50h TEST1 = 1b: 00h
Table 49. Interrupt Line Register (3Ch) Bits 7:0 Field Interrupt Line R/W Read/Write 00h Reset/Description
Table 50. Interrupt Pin Register (3Dh) If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core. If TEST0 = 1b, interrupt B is used as the PCI interrupt for this core. Bits 7:0 Field Interrupt Pin R Read/Write Reset/Description TEST0 = 0b: 01h TEST0 = 1b: 02h
Table 51. Min_Gnt Register (3Eh) The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns. Bits 7:0 Min_Gnt Field R Read/Write 03h Reset/Description
Table 52. Max_Lat Register (3Fh) The USS-344 requires service at a minimum interval of 21.3 s. Bits 7:0 Max_Lat Field R Read/Write 56h Reset/Description
Table 53. Special--Subsystem Write Capability (4Ch) This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0 is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID registers (refer to Tables 23 and 24). Bits 31:1 0 Field Reserved Subsystem Write R R/W Read/Write Reset/Description 00000000h 0b 0 = Subsystem write disabled 1 = Subsystem write enabled
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
PCI Function 2--Single-Port USB Host Controller 2
Table 54. Vendor ID Register (00h--01h) This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG. Bits 15:0 Vendor ID Field R Read/Write Reset/Description Assigned 11C1h
Table 55. Device ID Register (02h--03h) This register is fixed as the Agere Systems product USS-344. Bits 15:0 Device ID Field R Read/Write Reset/Description Assigned 5803h
Table 56. Command Register (04h--05h) All read-only bits represent nonconfigurable features of the USS-344. Bits 0 1 2 3 4 5 6 7 8 9 15:10 Field IO Space Memory Space Bus Master Special Cycles Memory Write and Invalidate Enable VGA Palette Snoop Parity Error Response Wait Cycle Control SERRN Enable Fast Back-to-back Enable Reserved R/W R/W R/W R R/W R R/W R R/W R/W R Read/Write Reset/Description 0 0 0 0 0 0 0 0 0 0 000000b
Table 57. Status Register (06h--07h) All read-only bits represent nonconfigurable features of the USS-344. Bits 3:0 4 5 6 7 8 10:9 11 12 13 14 15 Reserved Capabilities 66 MHz Capable UDF Support Fast Back-to-back Capable Data Parity Error Detected DEVSEL Timing Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Field R R R R R R/W R R/W R/W R/W R/W R/W Read/Write Reset/Description 0000b TEST1 = 0b: 1 TEST1 = 1b: 0 0 0 0 0 01 0 0 0 0 0
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 58. Revision ID Register (08h) Represents the current revision of the USS-344. Bits 7:0 Field Revision ID* R Read/Write 10h Reset/Description
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 59. Class Code Register (09h--0Bh) The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification. Bits 7:0 15:8 23:16 Field Programming Interface R Subclass R Base Class R Read/Write Reset/Description 10h = OpenHCI Host Controller 03h = Universal Serial Bus 0Ch = Serial Bus Controller
Table 60. Cache Line Size Register (0Ch) No cache line is supported by the USS-344. Bits 7:0 Field Cache Line Size R Read/Write 00h Reset/Description
Table 61. Latency Timer Register (0Dh) Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master. Bits 7:0 Field Latency Timer R/W Read/Write Reset/Description Upper 5 bits are read/write. Lower 3 bits are read only.
Table 62. Header Type Register (0Eh) The USS-344 supports PCI header type 0 only. Bits 7:0 Field Header Type R Read/Write Reset/Description 80h = Multifunction PCI Device
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
Table 63. BIST Register (0Fh) BIST is not supported by the USS-344. Bits 7:0 BIST Field R Read/Write 00h Reset/Description
Table 64. Base Address Register 0 (10h--13h) The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device. As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K (212) memory size. Bits 31:0 BAR 0 Field R/W Read/Write Reset/Description Lower 12 bits are read only. Upper 20 bits are read/write.
Table 65. Base Address Register 1, 2, 3, 4, 5 (14h--17h), (18h--1Bh), (1Ch--1Fh), (20h--23h), (24h--27h) These Base Address registers are unused by the USS-344 device. Bits 31:0 Field BAR 1--5 R Read/Write Reset/Description 00000000h
Table 66. Cardbus CIS Pointer Register (28h--2Bh) Cardbus CIS pointer not required for the USS-344. Bits 31:0 Field CardBus CIS Pointer R Read/Write Reset/Description 00000000h
Table 67. Subsystem Vendor ID Register (2Ch--2Dh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem Vendor ID R/W Read/Write 11C1h Reset/Description
Table 68. Subsystem ID Register (2Eh--2Fh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem ID R/W Read/Write 5803h Reset/Description
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 69. Expansion ROM Base Address Register (30h--33h) Expansion ROM not supported by the USS-344. Bits 31:0 Field Expansion ROM Base Address R Read/Write Reset/Description 00000000h
Table 70. Capabilities Pointer Register (34h) Bits 7:0 Cap_Ptr Field R Read/Write Reset/Description TEST1 = 0b: 50h TEST1 = 1b: 00h
Table 71. Interrupt Line Register (3Ch) Bits 7:0 Field Interrupt Line R/W Read/Write 00h Reset/Description
Table 72. Interrupt Pin Register (3Dh) If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core. If TEST0 = 1b, interrupt C is used as the PCI interrupt for this core. Bits 7:0 Field Interrupt Pin R Read/Write Reset/Description TEST0 = 0b: 01h TEST0 = 1b: 03h
Table 73. Min_Gnt Register (3Eh) The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns. Bits 7:0 Min_Gnt Field R Read/Write 03h Reset/Description
Table 74. Max_Lat Register (3Fh) The USS-344 requires service at a minimum interval of 21.3 s. Bits 7:0 Max_Lat Field R Read/Write 56h Reset/Description
Table 75. Special--Subsystem Write Capability (4Ch) This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0 is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID registers (refer to Tables 23 and 24). Bits 31:1 0 Field Reserved Subsystem Write R R/W Read/Write Reset/Description 00000000h 0b 0 = Subsystem write disabled 1 = Subsystem write enabled
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
PCI Function 3--Single-Port USB Host Controller 3
Table 76. Vendor ID Register (00h--01h) This register is fixed as the Agere Systems vendor ID assigned by the PCI SIG. Bits 15:0 Field Vendor ID Read/Write R Reset/Description Assigned 11C1h
Table 77. Device ID Register (02h--03h) This register is fixed as the Agere Systems product USS-344. Bits 15:0 Field Device ID Read/Write R Reset/Description Assigned 5803h
Table 78. Command Register (04h--05h) All read-only bits represent nonconfigurable features of the USS-344. Bits 0 1 2 3 4 5 6 7 8 9 15:10 Field IO Space Memory Space Bus Master Special Cycles Memory Write and Invalidate Enable VGA Palette Snoop Parity Error Response Wait Cycle Control SERRN Enable Fast Back-to-back Enable Reserved Read/Write R/W R/W R/W R R/W R R/W R R/W R/W R 0 0 0 0 0 0 0 0 0 0 000000b Reset/Description
Table 79. Status Register (06h--07h) All read-only bits represent nonconfigurable features of the USS-344. Bits 3:0 4 5 6 7 8 10:9 11 12 13 14 15 24 Field Reserved Capabilities 66 MHz Capable UDF Support Fast Back-to-back Capable Data Parity Error Detected DEVSEL Timing Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Read/Write R R R R R R/W R R/W R/W R/W R/W R/W Reset/Description 0000b TEST1 = 0b: 1 TEST1 = 1b: 0 0 0 0 0 01 0 0 0 0 0 Agere Systems Inc.
Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 80. Revision ID Register (08h) Represents the current revision of the USS-344. Bits 7:0 Field Revision ID* R Read/Write 10h Reset/Description
* The revision of the USS-344 can be identified either electronically or by physical markings. The revision can be identified electronically using the standard PCI Revision ID register described in this table. The revision can also be identified by physical markings using the last letter of the USS-344 identifier code printed on the device. The USS-344 identifier code will be printed using the format USS344XY, where X will identify the package type (M or T) and Y will identify the revision.
Table 81. Class Code Register (09h--0Bh) The PCI class code for all OpenHCI host controllers is defined in the OpenHCI specification. Bits 7:0 15:8 23:16 Field Programming Interface R Subclass R Base Class R Read/Write Reset/Description 10h = OpenHCI Host Controller 03h = Universal Serial Bus 0Ch = Serial Bus Controller
Table 82. Cache Line Size Register (0Ch) No cache line is supported by the USS-344. Bits 7:0 Field Cache Line Size R Read/Write 00h Reset/Description
Table 83. Latency Timer Register (0Dh) Controls the number of clock cycles the USS-344 may remain on the PCI bus after becoming bus master. Bits 7:0 Field Latency Timer R/W Read/Write Reset/Description Upper 5 bits are read/write. Lower 3 bits are read only.
Table 84. Header Type Register (0Eh) The USS-344 supports PCI header type 0 only. Bits 7:0 Field Header Type R Read/Write Reset/Description 80h = Multifunction PCI Device
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Advance Data Sheet, Rev. 9 June 2001
PCI Registers (continued)
Table 85. BIST Register (0Fh) BIST is not supported by the USS-344. Bits 7:0 BIST Field R Read/Write 00h Reset/Description
Table 86. Base Address Register 0 (10h--13h) The Base Address register is used to specify to the PCI operating system the memory size of the USS-344 device. As recommended by the OpenHCI specification, the lower 12 bits are read only (fixed to logic 0) to indicate 4K (212) memory size. Bits 31:0 BAR 0 Field R/W Read/Write Reset/Description Lower 12 bits are read only. Upper 20 bits are read/write.
Table 87. Base Address Register 1, 2, 3, 4, 5 (14h--17h), (18h--1Bh), (1Ch--1Fh), (20h--23h), (24h--27h) These base address registers are unused by the USS-344 device. Bits 31:0 Field BAR 1--5 R Read/Write Reset/Description 00000000h
Table 88. Cardbus CIS Pointer Register (28h--2Bh) Cardbus CIS pointer not required for the USS-344. Bits 31:0 Field CardBus CIS Pointer R Read/Write Reset/Description 00000000h
Table 89. Subsystem Vendor ID Register (2Ch--2Dh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem Vendor ID R/W Read/Write 11C1h Reset/Description
Table 90. Subsystem ID Register (2Eh--2Fh) The subsystem vendor ID is R/W for compliance with Microsoft PC98 specifications. On reset, this register is read only. System BIOS may write a 1 to Special--Subsystem Write Capability register (4Ch) bit 0 to enable write capability of this register. After configuring this register, the system BIOS must write a 0 to Special--Subsystem Write Capability register (4Ch) bit 0 to disable write capability of this register. Bits 15:0 Field Subsystem ID R/W Read/Write 5803h Reset/Description
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
PCI Registers (continued)
Table 91. Expansion ROM Base Address Register (30h--33h) Expansion ROM not supported by the USS-344. Bits 31:0 Field Expansion ROM Base Address R Read/Write Reset/Description 00000000h
Table 92. Capabilities Pointer Register (34h) Bits 7:0 Cap_Ptr Field R Read/Write Reset/Description TEST1 = 0b: 50h TEST1 = 1b: 00h
Table 93. Interrupt Line Register (3Ch) Bits 7:0 Field Interrupt Line R/W Read/Write 00h Reset/Description
Table 94. Interrupt Pin Register (3Dh) If TEST0 = 0b, interrupt A is used as the PCI interrupt for this core. If TEST0 = 1b, interrupt D is used as the PCI interrupt for this core. Bits 7:0 Field Interrupt Pin R Read/Write Reset/Description TEST0 = 0b: 01h TEST0 = 1b: 04h
Table 95. Min_Gnt Register (3Eh) The USS-344 can support a four DWORD master burst read or write which requires less than 500 ns. Bits 7:0 Min_Gnt Field R Read/Write 03h Reset/Description
Table 96. Max_Lat Register (3Fh) The USS-344 requires service at a minimum interval of 21.3 s. Bits 7:0 Max_Lat Field R Read/Write 56h Reset/Description
Table 97. Special--Subsystem Write Capability (4Ch) This is a special register implemented for compliance with Microsoft PC98 Specification, Chapter 9, Item 11. Bit 0 is read/write to allow the system BIOS to enable write capability of the Subsystem Vendor ID and Subsystem ID registers (refer to Tables 23 and 24). Bits 31:1 0 Field Reserved Subsystem Write R R/W Read/Write Reset/Description 00000000h 0b 0 = Subsystem write disabled 1 = Subsystem write enabled
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Advance Data Sheet, Rev. 9 June 2001
USB Registers
Table 98. USB Operational Registers Summary Each PCI Function has one set of USB operational registers available through the memory mapped Base Address register 0. Each set of USB operational registers represents one single-port USB host controller. Refer to Tables 99--120 for more details on each of these registers. Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 100h 104h 108h 10Ch Register Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HceControl HceInput HceOutput HceStatus
Table 99. HcRevision Register (00h) Bits 7:0 8 Field Revision (REV) Legacy (L) Reset 10h 1b HCD HC (Host Controller Driver) (Host Controller) R R R R
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 100. HcControl Register (04h) Bits 1:0 2 3 4 5 7:6 Field Control Bulk Service Ratio (CBSR) Periodic List Enable (PLE) Isochronous Enable (IE) Control List Enable (CLE) Bulk List Enable (BLE) Host Controller Functional State (HCFS) 00b: UsbReset 01b: UsbResume 10b: UsbOperational 11b: UsbSuspend Interrupt Routing (IR) Remote Wakeup Connected (WC) Remote Wakeup Enable (RWE) Reset 00b 0b 0b 0b 0b 00b HCD HC (Host Controller Driver) (Host Controller) R/W R/W R/W R/W R/W R/W R R R R R R/W
8 9 10
0b 0b 0b
R/W R/W R/W
R R/W R
Table 101. HcCommandStatus Register (08h) Bits 0 1 2 3 17:16 Field Host Controller Reset (HCR) Control List Filled (CLF) Bulk List Filled (BLF) Ownership Change Request (OCR) Scheduling Overrun Count (SOC) Reset 0b 0b 0b 0b 0b HCD R/W R/W R/W R/W R HC R/W R/W R/W R/W R/W
Table 102. HcInterruptStatus Register (0Ch) Bits 0 1 2 3 4 5 6 30 Field Scheduling Overrun (SO) Writeback Done Head (WDH) Start of Frame (SF) Resume Detected (RD) Unrecoverable Error (UE) Frame Number Overflow (FNO) Root Hub Status Change (RHSC) Ownership Change (OC) Reset 0b 0b 0b 0b 0b 0b 0b 0b HCD R/W R/W R/W R/W R/W R/W R/W R/W HC R/W R/W R/W R/W R/W R/W R/W R/W
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Advance Data Sheet, Rev. 9 June 2001
USB Registers (continued)
Table 103. HcInterruptEnable Register (10h) Bits 0 Field Scheduling Overrun (SO) 0--Ignore 1--Enable interrupt Writeback Done Head (WDH) 0--Ignore 1--Enable interrupt Start of Frame (SF) 0--Ignore 1--Enable interrupt Resume Detected (RD) 0--Ignore 1--Enable interrupt Unrecoverable Error (UE) 0--Ignore 1--Enable interrupt Frame Number Overflow (FNO) 0--Ignore 1--Enable interrupt Root Hub Status Change (RHSC) 0--Ignore 1--Enable interrupt Ownership Change (OC) 0--Ignore 1--Enable interrupt Master Interrupt Enable (MIE) 0--Ignored by HC 1--Enables interrupt generation due to events specified in the other bits of this register Reset 0b HCD HC (Host Controller Driver) (Host Controller) R/W R
1
0b
R/W
R
2
0b
R/W
R
3
0b
R/W
R
4
0b
R/W
R
5
0b
R/W
R
6
0b
R/W
R
30
0b
R/W
R
31
0b
R/W
R
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 104. HcInterruptDisable Register (14h) Bits 0 Field Scheduling Overrun (SO) 0--Ignore 1--Disable interrupt generation Writeback Done Head (WDH) 0--Ignore 1--Disable interrupt Start of Frame (SF) 0--Ignore 1--Disable interrupt Resume Detected (RD) 0--Ignore 1--Disable interrupt Unrecoverable Error (UE) 0--Ignore 1--Disable interrupt Frame Number Overflow (FNO) 0--Ignore 1--Disable interrupt Root Hub Status Change (RHSC) 0--Ignore 1--Disable interrupt Ownership Change (OC) 0--Ignore 1--Disable interrupt Master Interrupt Enable (MIE) 0--Ignored by HC 1--Disables interrupt generation due to events specified in the other bits of this register Reset 0b HCD HC (Host Controller Driver) (Host Controller) R/W R
1
0b
R/W
R
2
0b
R/W
R
3
0b
R/W
R
4
0b
R/W
R
5
0b
R/W
R
6
0b
R/W
R
30
0b
R/W
R
31
0b
R/W
R
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Advance Data Sheet, Rev. 9 June 2001
USB Registers (continued)
Table 105. HcHCCA Register (18h) Bits 31:8 Field Host Controller Communications Area (HCCA) Base Address Bits 7:0 will always return a 0. Table 106. HcPeriodCurrentED Register (1Ch) Bits 31:4 Field Period Current ED (PCED) Base Address Bits 3:0 will always return a 0. Table 107. HcControlHeadED Register (20h) Bits 31:4 Field Control Head ED (CHED) Base Address Bits 3:0 will always return a 0. Table 108. HcControlCurrentED Register (24h) Bits 31:4 Field Control Current ED (CCED) Base Address Bits 3:0 will always return a 0. Table 109. HcBulkHeadED Register (28h) Bits 31:4 Field Bulk Head ED (BHED) Base Address Bits 3:0 will always return a 0. Table 110. HcBulkCurrentED Register (2Ch) Bits 31:4 Field Bulk Current ED (BCED) Base Address Bits 3:0 will always return a 0. Table 111. HcDoneHead Register (30h) Bits 31:4 Field Done Head ED (DH) Base Address Bits 3:0 will always return a 0. Reset 0h HCD R HC R/W Reset 0h HCD R/W HC R/W Reset 0h HCD R/W HC R Reset 0h HCD R/W HC R/W Reset 0h HCD R/W HC R Reset 0h HCD R/W HC R Reset 0h HCD HC (Host Controller Driver) (Host Controller) R/W R
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
USB Registers (continued)
Table 112. HcFmInterval Register (34h) Bits 13:0 30:16 31 Field Frame Interval (FI) FS Largest Data Packet (FSMPS) Frame Interval Toggle (FIT) Reset 2EDFh 0h 0b HCD HC (Host Controller Driver) (Host Controller) R/W R/W R/W R R R
Table 113. HcFmRemaining Register (38h) Bits 13:0 31 Field Frame Remaining (FR) Frame Remaining Toggle (FRT) Reset 0h 0b HCD R R HC R/W R/W
Table 114. HcFmNumber Register (3Ch) Bits 15:0 Field Frame Number (FN) Reset 0h HCD R HC R/W
Table 115. HcPeriodicStart Register (40h) Bits 13:0 Periodic Start (PS) Field Reset 0h HCD R/W HC R
Table 116. HcLSThreshold (44h) Bits 11:0 LS Threshold Field Reset 628h HCD R/W HC R
Table 117. HcRhDescriptorA Register (48h) Bits 7:0 Field Reset 01h 1b 0b 0b 1b 0b 10h HCD R R/W R/W R R/W R/W R/W HC R R R R R R R
Number Downstream Ports (NDP) 8 Power Switching Mode (PSM) 9 No Power Switching (NPS) 10 Device Type (DT) 11 Overcurrent Protection Mode (OCPM) 12 No Overcurrent Protection (NOCP) 24:31 Power On to Power Good Time (POTPGT)
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USB Registers (continued)
Table 118. HcRhDescriptorB Register (4Ch) Bits 15:0 17:16 Field Device Removable (DR) Port Power Control Mask (PPCM) Reset 0000h 0002h HCD HC (Host Controller Driver) (Host Controller) R/W R/W R R
Table 119. HcRhStatus Register (50h) Bits 0 1 15 16 17 31 Field Local Power Status (LPS) Overcurrent Indicator (OCI) Device Remote Wakeup Enable (DRWE) Local Power Status Change (LPSC) Overcurrent Indicator Change (OCIC) Clear Remote Wakeup Enable (CRWE) Reset 0b 0b 0b 0b 0b 0b HCD R/W R R/W R/W R/W W HC R R/W R R R/W R
Table 120. HcRhPortStatus1 Register (54h) Bits 0 1 2 3 4 8 9 16 17 18 19 20 Field Current Connect Status (CCS) Port Enable Status (PES) Port Suspend Status (PSS) Port Overcurrent Indicator (POCI) Port Reset Status (PRS) Port Power Status (PPS) Low-speed Device Attached (LSDA) Connect Status Change (CSC) Port Enable Status Change (PESC) Port Suspend Status Change (PSSC) Port Overcurrent Indicator Change (OCIC) Port Reset Status Change (PRSC) Reset 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b HCD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Legacy Support Registers
The legacy support function and all registers described in this section are available on all four embedded USB host controllers. Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. The offset of these registers is relative to the base address of the respective host controller core operational registers with HceControl located at offset 100h. Table 121. Legacy Support Registers Offset 100h 104h 108h 10Ch Register HceControl HceInput HceOutput HceStatus Description Used to enable and control the emulation hardware and report various status information. Emulation side of the Legacy Input Buffer register. Emulation side of the Legacy Output Buffer register where keyboard and mouse data is to be written by software. Emulation side of the Legacy Status register.
Three of the operational registers (HceStatus, HceInput, HceOutput) are accessible at I/O address 60h and 64h when emulation is enabled. Reads and writes to the registers using I/O addresses have side effects as outlined in the Table 122. Table 122. Emulated Registers I/O Address 60h 60h 64h 64h Cycle Type IN OUT IN OUT Register Contents Accessed/Modified HceOutput HceInput HceStatus HceInput Side Effects IN from port 60h will set OutputFull in HceStatus to 0. OUT to port 60h will set InputFull to 1 and CmdData to 0 in HceStatus. IN from port 64h returns current value of HceStatus with no other side effect. OUT to port 64h will set InputFull to 0 and CmdData in HceStatus to 1.
HceInput Register
Table 123. HceInput Register (104h) Bit 7:0 31:8 Field InputData Reserved R/W R/W -- Description This register holds data that is written to I/O ports 60h and 64h. --
I/O data that is written to ports 60h and 64h is captured in this register when emulation is enabled. This register may be read or written directly by accessing it with its memory address in the host controller's operational register space. When accessed directly with a memory cycle, reads and writes of this register have no side effects.
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Legacy Support Registers (continued)
HceOutput Register
Table 124. HceOutput Register (108h) Bit 7:0 31:8 Field OutputData Reserved R/W R/W -- Description This register hosts data that is returned when an I/O read of port 60h is performed by application software. --
The data placed in this register by the emulation software is returned when I/O port 60h is read and emulation is enabled. On a read of this location, the OutputFull bit in HceStatus is set to 0.
HceStatus Register
Table 125. HceStatus Register (10Ch) Bit 0 Field OutputFull R/W R/W Description The HC sets this bit to 0 on a read of I/O port 60h. If IRQEn is set and AuxOutputFull is set to 0, then an IRQ1 is generated as long as this bit is set to 1. If IRQEn is set and AuxOutputFull is set to 1, then an IRQ12 is generated as long as this bit is set to 1. While this bit is 0 and CharacterPending in HceControl is set to 1, an emulation interrupt condition exists. Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write to address 60h or 64h. While this bit is set to 1 and emulation is enabled, an emulation interrupt condition exists. Nominally used as a system flag by software to indicate a warm or cold boot. The HC sets this bit to 0 on an I/O write to port 60h and to 1 on an I/O write to port 64h. This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is not inhibited. IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and the IRQEn bit is set. Used to indicate a time-out. Indicates parity error on keyboard/mouse data. --
1
InputFull
R/W
2 3 4 5 6 7 31:8
Flag CmdData Inhibit Switch AuxOutputFull Time-out Parity Reserved
R/W R/W R/W R/W R/W R/W --
The contents of the HceStatus register are returned on an I/O Read of port 64h when emulation is enabled. Reads and writes of port 60h and writes to port 64h can cause changes in this register. Emulation software can directly access this register through its memory address in the host controller's operational register space. Accessing this register through its memory address produces no side effects.
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Legacy Support Registers (continued)
HceControl Register
Table 126. HceControl Register (100h) Bit 0 Field EmulationEnable Reset 0b R/W R/W Description When set to 1, the HC is enabled for legacy emulation. The HC decodes accesses to I/O registers 60h and 64h and generates IRQ1 and/or IRQ12 when appropriate. Additionally, the HC generates an emulation interrupt at appropriate times to invoke the emulation software. This bit is a static decode of the emulation interrupt condition. When set, an emulation interrupt is generated when the OutputFull bit of the HceStatus register is set to 0. When set, the HC generates IRQ1 or IRQ12 as long as the OutputFull bit in HceStatus is set to 1. If the AuxOutputFull bit of HceStatus is 0, then IRQ1 is generated; if it is 1, then an IRQ12 is generated. When set to 1, IRQ1 and IRQ12 from the keyboard controller causes an emulation interrupt. The function controlled by this bit is independent of the setting of the EmulationEnable bit in this register. Set by HC when a data value of D1h is written to I/O port 64h. Cleared by HC on write to I/O port 64h of any value other than D1h. Indicates that a positive transition on IRQ1 from keyboard controller has occurred. SW may write a 1 to this bit to clear it (set it to 0). SW write of a 0 to this bit has no effect. Indicates that a positive transition on IRQ12 from keyboard controller has occurred. SW may write a 1 to this bit to clear it (set it to 0). SW write of a 0 to this bit has no effect. Indicates current state of gate A20 on keyboard controller. Used to compare against value written to 60h when GateA20Sequence is active. Must read as 0s. connecting the VIO signal to the signaling voltage on the motherboard or VIO pin on the card edge of the expansion card. The VIO pin will select the PCI signaling level as indicated in Table 127. A 5 V reference voltage is not required for the USS-344 to be 5 V compatible. Table 127. PCI Signaling Levels VIO Pin Input Voltage 4.75 V--5.25 V 3.0 V--3.6 V USS-344 PCI Signaling Level (All PCI Signals) 5 V signaling 3.3 V signaling
1 2 3
EmulationInterrupt CharacterPending IRQEn
-- 0b 0b
R R/W R/W
4
ExternalIRQEn
0b
R/W
5
GateA20Sequence
0b
R/W
6
IRQ1Active
0b
R/W
7
IRQ12Active
0b
R/W
8
A20State
0b
R/W
31:9
Reserved
--
--
Connection Instructions
Figure 6 shows a typical connection of the USS-344 to provide four USB ports and full legacy support to a PCI-based system. For each of the following sections, refer to Figure 6 for guidance.
PCI Connection Instructions
The USS-344 interfaces directly with any 32-bit, 33 MHz PCI bus simply by connecting all PCI related signals directly to the signals on the host motherboard or card edge of an expansion card. The PCI signaling level for all PCI signals of the USS-344 is selected by Agere Systems Inc.
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Connection Instructions (continued)
USB Connection Instructions
The USS-344 is a port-powered OHCI host controller (refer to OHCI specification) requiring an external switchable power regulator to supply downstream USB port power controlled by the USS-344. The power regulator interface has been designed to interface directly with commonly used USB power regulators with very little additional circuitry. The PRTPWR[0, 1, 2, 3] output signal is used as the switch for the power regulator. The PRTPWR[0, 1, 2, 3] signal must be bootstrapped with a pull-up or pull-down resistor to select the appropriate power switch polarity. Bootstrapping with a pull-up resistor will select an active-low power switch while bootstrapping with a pull-down will select an active-high power switch. Figure 3 depicts a typical board connection for both power regulator enable polarities. The PWRFLT[0, 1, 2, 3]N can be connected directly to an active-low power fault regulator output to inform the USS-344 of a USB port overcurrent condition. DPLS[0, 1, 2, 3] and DMNS[0, 1, 2, 3] are related to the integrated USB transceiver and are connected directly to the USB port connector through a 28 --32 series resistor for each signal. Figure 5 shows complete detail of the USS-344 connection to USB. CLK48 must be connected to a 48 MHz oscillator to provide a suitable USB clock to the USS-344. If CLK48STOP signal is used to disable the external oscillator during D3 Power Management state, CLK48STOP must be bootstrapped with a pull-up or pull-down resistor to select the appropriate disable polarity. Bootstrapping with a pull-up resistor will select an active-low disable while bootstrapping with a pulldown will select an active-high disable. Figure 4 depicts a typical board connection for both oscillator enable polarities. CLK48STOP must be pulled to a stable logic value with a resistor if CLK48STOP is not used. Figure 4 also shows the typical board connection when CLK48STOP is not used.
Test Mode Connection Instructions
TEST[3:0] input pins present various options and test modes for the USS-344. These pins can be connected directly to VDD or ground as needed. One test mode (NAND tree mode) is available for a system designer to implement. For a system designer who wishes to implement NAND tree mode, it is recommended that a pull-down resistor be used on TEST2 input. This will allow an in-circuit tester to drive TEST2 high and activate NAND tree mode (see NAND Tree Mode section). TEST3, TEST1, and TEST0 can be grounded without a resistor. It is also recommended that all NAND tree pins have a corresponding PWB trace that can be driven by the incircuit tester during NAND tree mode. Table 128. Test Mode Decodes TEST[3:0] 00X0 Description Share Interrupt A. All four controllers return a 01h in the Interrupt Pin register (3Dh) and use the PCI interrupt A pin. Individual Interrupt. Controller 0 returns 01h in the Interrupt Pin register (3Dh) and uses the PCI interrupt A pin. Controller 1 returns 02h in the interrupt pin register (3Dh) and uses the PCI interrupt B pin. Controller 2 returns 03h in the Interrupt Pin register (3Dh) and uses the PCI interrupt C pin. Controller 3 returns 04h in the Interrupt Pin register (3Dh) and uses the PCI interrupt D pin. Power Management Interface Enabled. Power management interface enabled in all four controllers. Power Management Interface Disabled. Power management interface disabled in all four controllers. NAND Test.
00X1
000X
001X
01XX
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Connection Instructions (continued)
5 Vdc-5 Vdc SWITCHED REGULATOR USS-344 PRTPWRX 2 k 2 k EN ACTIVEHIGH ENABLE USS-344 PRTPWRX EN ACTIVELOW ENABLE
5-8738.r1
5 Vdc-5 Vdc SWITCHED REGULATOR
Figure 3. Typical Board Connection for Both Power Regulator Enable Polarities
48 MHz OSCILLATOR USS-344 CLK48STOP 2 k 2 k EN ACTIVELOW ENABLE USS-344 CLK48STOP
48 MHz OSCILLATOR EN ACTIVEHIGH ENABLE
USS-344
CLK48STOP 2 k
5-8739
Figure 4. Typical Board Connection for Both Oscillator Enable Polarities or Without Oscillator
USB CONNECTOR DPLS INTEGRATED USB TRANSCEIVER 28 --32
15 k 5%
DMNS 28 --32
DOWNSTREAM PORT
INTEGRATED USB TRANSCEIVER
15 k 5%
5-9289
Figure 5. USB Transceiver Connection Agere Systems Inc. 39
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Advance Data Sheet, Rev. 9 June 2001
Legacy Configuration
Also included in the USS-344 is the legacy PS/2 mouse and keyboard interface as defined in the OpenHCI Open Host Controller Interface Specification for USB Release 1.0a. This legacy interface along with standard USB BIOS drivers allows USB mice and keyboards to operate in MS-DOS* mode. Legacy support need not be implemented by the system designer if not desired. If not implemented, A20I, MIRQ12I, and KIRQ12I must be connected to a stable logic level. Figure 6 shows the typical legacy support connection to the USS-344. Figure 7 shows the typical connection of the unused legacy support signals when legacy support is not desired.
3.3 Vdc CLK48 CLK48STOP 5 Vdc
48 MHz OSC
PRTPWR0 PWRFLT0N
5 Vdc-5 Vdc SWITCHED REGULATOR
VBUS = 5 Vdc DPLS0/DMNS0 USB CONNECTOR
PRTPWR1 PWRFLT1N PCI VIO AGERE USS-344 PCI-TO-USB OHCI HOST CONTROLLER
5 Vdc-5 Vdc SWITCHED REGULATOR
VBUS = 5 Vdc DPLS1/DMNS1 USB CONNECTOR
PCI BUS
CPU
PCI SIGNALS 32-bit, 33 MHz
PRTPWR2 PWRFLT2N
5 Vdc-5 Vdc SWITCHED REGULATOR
VBUS = 5 Vdc DPLS2/DMNS2 USB CONNECTOR
PMEN PRTPWR3 PWRFLT3N 5 Vdc-5 Vdc SWITCHED REGULATOR VBUS = 5 Vdc DPLS3/DMNS3 USB CONNECTOR
SMI A20MN
8259 INTERRUPT CONTROLLER
IRQ1 IRQ12
KIRQ1I MIRQ12I A2OI
8042 LEGACY DEVICE CONTROLLER
PS/2 MOUSE
PS/2 KEYBOARD
OPTIONAL LEGACY SUPPORT
5-7829
Figure 6. Typical Legacy Support Connection
* MS-DOS is a registered trademark of Microsoft Corporation.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Legacy Configuration (continued)
3.3 Vdc CLK48 CLK48STOP PRTPWR0 PWRFLT0N 5 Vdc
48 MHz OSC
5 Vdc-5 Vdc SWITCHED REGULATOR
VBUS = 5 Vdc
USB CONNECTOR
DPLS0/DMNS0 5 Vdc-5 Vdc SWITCHED REGULATOR VBUS = 5 Vdc USB CONNECTOR DPLS1/DMNS1 5 Vdc-5 Vdc SWITCHED REGULATOR
PRTPWR1 PWRFLT1N PCI VIO AGERE USS-344 PCI-TO-USB OHCI HOST CONTROLLER PRTPWR2 PWRFLT2N
PCI BUS
VBUS = 5 Vdc
CPU
PCI SIGNALS 32-bit, 33 MHz
USB CONNECTOR
DPLS2/DMNS2 PMEN PRTPWR3 PWRFLT3N
5 Vdc-5 Vdc SWITCHED REGULATOR
VBUS = 5 Vdc
USB CONNECTOR
DPLS3/DMNS3 MIRQ12I 2 k 2 k A20MN IRQ1 KIRQ1I 2 k IRQ12 SMIN A201
5-8740
Figure 7. Typical Connection When Not Using Legacy Support
Power Connection Recommendations
The USS-344 is a 3.3 V device. Therefore, all VDD inputs must be connected to an appropriate 3.3 V source. VDDT provides all transceiver power and must be connected to a 3.3 V source. It is recommended that the system designer undertake special board routing and filtering of VDDT and VSST to isolate these power inputs from noise induced by other components.
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Power Management Interface
An advanced power management capabilities interface compliant with PCI Bus Power Management Interface Specification Revision 1.1 has been incorporated into each of the USS-344 controllers. This interface allows the USS-344 to be placed in various power management states offering a variety of power savings for a host system. Table 129 highlights the USS-344 support for power management states and features supported for each of the power management states. The USS-344 has the ability to internally gate-off the CLK48 input, disable the USB transceivers, and assert USB resume signaling asynchronously (without active CLK48) in response to upstream USB resume being detected. The USS-344 will assert PMEN and retain chip context in accordance with the rules defined in the PCI Bus Power Management Interface Specification Revision 1.1. Table 129. USS-344 Support for Power Management States
Power State Management Required/ State Optional D0 Required Clk48 Active Internally X CLK48 STOP Active USB Transciever Active X Async Resume Logic Active -- PMEN Assert Enabled -- Chip Context Maintained X Comments
D1
Optional
X
X
--
X
X
D2
Optional
--
--
X*
X
X
D3hot
Required
--
X
--
X*
X
--
D3cold
Required
--
--
--
--
--
Fully awake backwards compatible state. All logic in fullpower mode. Fully awake state with PCI bus master capabilities turned off by host. All logic in fullpower mode because of low latency returning to D0 State. USB sleep state with PCI bus master capabilities turned off by host. PCI clocks may be turned off by the system. Deep USB sleep state with PCI bus master capabilities turned off by host. PCI clocks may be turned off by the system. Fully asleep backwards compatible state. All power turned off. Reset required to recover to D0 state. All downstream devices disconnected because of power loss.
* Asynchronous resume logic active only when PME_Enable register bit is active.
A wakeup event (power management event) detected by a USB host controller is considered either an upstream resume detected or a connect status change (device disconnecting/connecting) detected. Any of these events detected by the USS-344 while the power management event is enabled will cause PMEN to be issued. This power management feature is considered an extension of the PCI Specification and is only present when enabled by the TEST1 input pin. While the TEST1 input pin is logic 0 (or ground), the power management function is enabled, the Power Management registers and Capabilities Pointer register are accessible, and the PCI Configuration Space Status register, bit 4, will read as logic 1 (capabilities list present). While the TEST1 input pin is logic 1, the power management function is disabled, the Power Management registers and Capabilities Pointer register are inaccessible and read as 0h, and the PCI Configuration Space Status register, bit 4, will read as logic 0 (no capabilities list).
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Power Management Interface (continued)
The CLK48STOP output pin is active if all four PCI cores in the USS-344 multifunction PCI device have been placed into the D3hot state. This will allow the external 48 MHz oscillator to be disabled and in a low-power mode while in this state. CLK48STOP is only active in D3hot state since this is the only low-power state with sufficient state-change latency to allow the external oscillator to be stopped. PMEN is an open collector output allowing wire-OR of several PMEN signals. The following Power Management register definitions present the specific implementation of the PCI Bus Power Management Interface Specification for the USS-344. All the following registers are located in the PCI configuration memory space of each controller in the USS-344. All further information concerning the register functions and the system implementation of this interface should be referenced from the PCI Bus Power Management Interface Specification Revision 1.1 available from the PCI Special Interest Group.
Configuration Space Offset 50h
Table 130. Capabilities Identifier (Cap_ID) Register Bits 7:0 Default Value 01h Read/Write R Description This capability is for the PCI power management data structure.
Configuration Space Offset 51h
Table 131. Next Item Pointer Register Bits 7:0 Default Value 00h Read/Write R Description No other PCI capabilities are implemented.
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Power Management Interface (continued)
Configuration Space Offset 52h
Table 132. Power Management Capabilities Register Bits 15:11 Default Value 01110b Read/ Write R Name/Description PME_Support. Specifies the states in which the PME signal can be asserted. XXXX0b--PME cannot be asserted in D0 state. XXX1Xb--PME can be asserted in D1 state. XX1XXb--PME can be asserted in D2 state. X1XXXb--PME can be asserted in D3hot state. 0XXXXb--PME cannot be asserted in D3cold state. D2_Support. This device supports the D2 power management state. D1_Support. This device supports the D1 power management state. Aux_Current. PMEN generation is not supported by this function. Therefore, this register is not applicable and returns 000b. DSI. No device specific initialization sequence is required before using this device. Reserved. PME Clock. No clocks are required for this device to issue PMEN. Version. PCI Power Management Interface Specification Revision 1.1 compliant.
10 9 8:6 5 4 3 2:0
1b 1b 000b 0b 0b 0b 010b
R R R R R R R
Configuration Space Offset 54h
Table 133. Power Management Control/Status Register Bits 15 Default Value 0b Read/ Write Read/ WriteClear R R/W R/W R R/W Name/Description PME_Status. This bit is set when the function would normally assert the PMEN signal independent of the state of the PME_En bit. Writing a 1b to this bit will clear the PME_Status bit and force the function to stop asserting PMEN. Data Scale. Variable based upon data select. See Table 136. Data_Select. The system uses this register to select the appropriate data for reporting in the Data Scale register and Data register. PME_En. When active (1b), the function is enabled to assert PMEN. Reserved. Power_State. Represents the current power state of the function.
14:13 12:9 8 7:2 1:0
See Table 136 0000b 0b 000000b 00b
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Power Management Interface (continued)
Configuration Space Offset 56h
Table 134. Power Management Bridge Support Extensions Bits 7 6 5:0 Default Value 0b 0b 000000b Read/ Write R R R Name/Description BPCC_En (Bus Power/Clock Control Enable). This is not a PCI bridge function. B2_B3# (B2/B3 Support for D3hot). This is not a PCI bridge function. Reserved.
Configuration Space Offset 57h
Table 135. Data Register Bits 7:0 Default Value See Table 136 Read/ Write R Description Represents the amount of power dissipated or consumed in various power management states. Variable based upon data select. See Table 136.
Power Consumption/Dissipation Reporting
Table 136. Power Consumption/Dissipation Reporting Value In Data Select 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b--1111b Data Reported D0 Power Consumed D1 Power Consumed D2 Power Consumed D3 Power Consumed D0 Power Dissipated D1 Power Dissipated D2 Power Dissipated D3 Power Dissipated Reserved (single-function PCI device configuration) Data 1Fh 38h 66h 07h 37h 37h 64h 03h 00000000b Data Scale 01b 10b 11b 11b 10b 10b 11b 11b 00b Units (Interpreting Data Scale) mW * 100 mW * 100 mW mW mW * 10 mW * 10 mW mW NA
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NAND Tree Mode
The USS-344 can be placed in a NAND tree mode of operation for board-level production testing. The NAND tree is designed to allow board-level contact testing of inputs and bidirectional pins of the USS-344. To activate the NAND tree in the USS-344, force pin 63 (TEST2) to a logic high and force pin 64 (TEST3) to a logic low. Pins 62 and 61 (TEST1 and TEST0) may be high or low. No clocks are required. When this is performed, the NAND tree will be active and follow the order of the map presented in Table 137. Figure 8 shows the NAND tree logic structure. The test mode connection instructions should be followed to place the USS-344 in NAND tree mode. Table 137. NAND Tree
Order Assignment 1 (Start) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Number 81 83 75 76 77 78 79 89 90 91 92 95 96 97 98 101 102 103 104 105 108 109 110 111 113 115 116 119 120 121 122 125 126 127 128 3 4 5 6 7 Pin Name CLK48STOP XLO/CLK48 SMIN PRTPWR0 PWRFLT0N PRTPWR1 PWRFLT1N DPLS0 DMNS0 DPLS1 DMNS1 DPLS2 DMNS2 DPLS3 DMNS3 PRTPWR2 PWRFLT2N PRTPWR3 PWRFLT3N INTAN INTBN INTCN INTDN RSTN CLK GNTN REQN PMEN AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BEN3 IDSEL AD23 AD22 Order Assignment 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Output Pin Pin Number 10 11 12 13 16 17 18 19 22 23 24 25 26 29 30 31 32 35 36 37 38 41 42 43 44 47 48 49 50 53 54 55 56 67 68 69 70 71 72 Pin Name AD21 AD20 AD19 AD18 AD17 AD16 C/BEN2 FRAMEN IRDYN TRDYN DEVSELN STOPN PERRN SERRN PAR C/BEN1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BEN0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 MIRQ12I KIRQ1I A20I A20MN IRQ1 IRQ12
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
NAND Tree Mode (continued)
CLK48STOP
VDD
CLK48
SMIN
PRTPWR0
PWRFLT0N
A20MN
IRQ1
IRQ12
5-7276a
Figure 8. NAND Tree Logic Structure
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Absolute Maximum Ratings
Table 138. Absolute Maximum Ratings Parameter Ambient Operating Temperature Range Storage Temperature Voltage on Any Pin with Respect to Ground VDD VDDT VIO (3.3 V operation) VIO (5 V operation) Symbol TA Tstg -- -- -- -- -- Min 0 -40 VSS - 0.3 3.0 3.135 3.0 4.75 Max 70 125 5.5 3.6 3.465 3.6 5.25 Unit C C V V V V V
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Electrical Characteristics
Table 139. Power Dissipation Parameter Power Dissipation Symbol PD Min 283 Typ 345 Max 410 Unit mW
PCI Electrical Characteristics
PCI Timing Specifications The clock waveform must be delivered to each PCI component in the system. In the case of expansion boards, compliance with the clock specification is measured at the expansion board component, not at the connector slot. Figure 9 shows the clock waveform and required measurement points for both 5 V and 3.3 V signaling environments. Table 140 summarizes the clock specifications.
5 V CLOCK 2.0 V 1.5 V 0.5 V 2.4 V 2 Vp-p (MINIMUM) 0.4 V tCYC tHIGH 3.3 V CLOCK 0.5VCC 0.4VCC 0.3VCC 0.6VCC tLOW 0.4VCC Vp-p (MINIMUM) 0.2VCC
5-6474
Figure 9. Clock Waveforms
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Electrical Characteristics (continued)
PCI Timing Parameters Table 140. Clock and Reset Specifications Symbol tCYC tHIGH tLOW -- -- Parameter CLK Cycle CLK High Time CLK Low Time CLK Slew Rate2 RSTN Slew Rate3 Time1 Min 30 11 11 1 50 Max -- -- 4 -- Unit ns ns ns V/ns mV/ns
1. In general, all PCI components must work with any clock frequency between nominal dc and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system, as long as the clock edges remain clean (monotonic), and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. A variance on this specification is allowed for components designed for use on the system motherboard only. These components may operate at any single fixed frequency up to 33 MHz and may enforce a policy of no frequency changes. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform, as shown in Figure 9. 3. The minimum RSTN slew rate applies only to the rising (deassertion) edge of the reset signal and ensures that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range.
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Electrical Characteristics (continued)
Table 141. 5 V and 3.3 V PCI Timing Parameters Symbol tVAL tVAL(ptp) tON tOFF tSU tSU(ptp) tH tRST tRST-CLK tRST-OFF tRRSU tRRH Parameter CLK to Signal Valid Delay--Bused CLK to Signal Valid Delay--Point to Point1, 2, 3 Float to Active Delay1, 7 Active to Float Delay1, 7 Input Setup Time to CLK--Bused Signals3, 4 Input Setup Time to CLK--Point to Point3, 4 Input Hold Time from CLK4 Reset Active Time After Power Stable5 Reset Active Time After CLK Stable5 Reset Active to Output Float Delay5, 6, 7 REQN to RSTN Setup Time RSTN to REQN Hold Time Signals1, 2, 3 Min 2 2 2 -- 7 10, 12 0 1 100 -- 10 x tCYC 0 Max 11 12 -- 28 -- -- -- -- -- 40 -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns
1. See the timing measurement conditions in Figure 4-8 of PCI Specification Revision 2.1. 2. For parts compliant to the 5 V signaling environment: Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load. Actual test capacitance may vary, but results should be correlated to these specifications. Note that faster buffers may exhibit some ring back when attached to a 50 pF lump load, which should be of no consequence as long as the output buffers are in full compliance with slew rate and V/I curve specifications. For parts compliant to the 3.3 V signaling environment: Minimum times are evaluated with same load used for slew rate measurement (see PCI Specification, Rev. 2.1s); maximum times are evaluated with the following load circuits, for high-going and low-going edges, respectively. TVAL(MAX) RISING EDGE PIN OUTPUT BUFFER 25 10 pF 10 pF 25 1/2 IN. MAX. TVAL(MAX) FALLING EDGE 1/2 IN. MAX. VCC
3. REQN and GNTN are point-to-point signals and have different output valid delay and input setup times than bused signals. GNTN has a setup time of 10 ns; REQN has a setup time of 12 ns. All other signals are bused. 4. See the timing measurement conditions in Figure 4-8 of PCI Specification Revision 2.1. 5. RSTN is asserted and deasserted asynchronously with respect to CLK. 6. All output drivers must be asynchronously floated when RSTN is active. 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Electrical Characteristics (continued)
USB Electrical Characteristics
Table 142. Full-Speed Source USB Electrical Characteristics Parameter Driver Characteristics Transition Time4, 5: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Driver Output Resistance Data Source Timings Full-speed Data Rate Frame Interval tR tF tRFM VCRS ZDRV tDRATE tFRAME CL = 50 pF CL = 50 pF (TR/TF) -- Steady-State Drive Average Bit Rate (12 Mbits/s 0.25%) 1.0 ms 0.05% 4 4 90 1.3 28 11.97 0.9995 20 20 110 2.0 43 12.03 1.0005 ns ns % V Mbits/s ms Symbol Conditions1, 2, 3 Min Max Unit
1. All voltages measured from the local ground potential, unless otherwise specified. 2. All timings use a capacitive load (CL) to ground of 50 pF, unless otherwise specified. 3. Full-speed timings have a 1.5 k pull-up to 2.8 V on the D+ data line. 4. Measured from 10% to 90% of the data signal. 5. The rising and falling edges should be smoothly transitioning (monotonic).
Table 143. Low-Speed Source USB Electrical Characteristics Parameter Driver Characteristics Transition Time1, 2: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Data Source Timings Low-speed Data Rate tR tF tRFM VCRS tDRATE CL = 50 pF CL = 350 pF CL = 50 pF CL = 350 pF (TR/TF) -- Average Bit Rate (1.5 Mbits/s 1.5%) 75 -- 75 -- 80 1.3 1.4775 -- 300 -- 300 120 2.0 1.5225 ns ns ns ns % V Mbits/s Symbol Conditions Min Max Unit
1. Measured from 10% to 90% of the data signal. 2. The rising and falling edges should be smoothly transitioning (monotonic).
Table 144. CLK48 Clock Specification Parameter CLK Cycle Time CLK High Time CLK Low Time Symbol tCYC tHIGH tLOW Min 20.8 - 0.01% 8.32 8.32 Max 20.8 + 0.01% 12.48 12.48 Unit ns ns ns
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Advance Data Sheet, Rev. 9 June 2001
USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Physical Markings
Each USS-344 will be physically marked as follows:
USS344 X Y
REVISION IDENTIFICATION. i.e., B IS USS-344 REVISION B PACKAGE TYPE. USS-344 DEVICE
5-8116a
T: 128-PIN TQFP
Outline Diagram
128-Pin TQFP
Dimensions are in millimeters.
16.00 0.20 14.00 0.20 PIN #1 IDENTIFIER ZONE
128 103
1.00 REF
1
102
0.25 GAGE PLANE SEATING PLANE 0.45/0.75 DETAIL A
20.00 0.20 22.00 0.20
0.106/0.200 0.19/0.27
38 65
0.08
M
39
64
DETAIL B
DETAIL A
DETAIL B
1.40 0.05 1.60 MAX SEATING PLANE 0.08
5-4427
0.50 TYP
0.05/0.15
Agere Systems Inc.
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USS-344 QuadraBus Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9 June 2001
Ordering Information
Device Code USS344S-DB Package 128-Pin TQFP Comcode 108556937
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@micro.lucent.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. QuadraBus is a trademark of Agere Systems Inc.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A.
June 2001 DS99-330CMPR-9 (Replaces DS99-330CMPR-8)

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